Networking Silicon L1-L7
Networking Silicon — 4 vendors and operators, each broken down by layer L1 to L7: what they sell at that layer, and which layer is their home turf.
Broadcom
Home turf: L2 / L3
L1 Physical
A chip's core physical-layer component is the SerDes (serialiser/deserialiser) — the circuitry converting the chip's internal parallel data into high-speed serial signals for transmission and reconstructing received signals back again.
L2 Data Link
This is one of this domain's star layers, because what a switch chip does at this layer is its entire reason for existing: performing MAC address learning, table lookup and then moving frames from ingress to the correct egress port — all at line rate in hardware with no software involvement.
L3 Network
This is this domain's second star layer, covering a frequently overlooked but critical fact: whether a device can carry the full internet routing table depends on the table capacity of the chip inside it, not on software or memory.
L4 Transport
The chip does not terminate TCP connections at this layer (that is the host's job), but it performs one task with enormous influence on transport-layer behaviour: implementing congestion signalling and queue management in hardware.
L5 Session
This layer is explicitly empty — no product or service. A switch chip is a stateless forwarding component processing packets against table entries and neither maintaining nor understanding application-level session concepts — session state belongs to hosts or to dedicated stateful devices (such as the firewall products of this site's Palo Alto and Fortinet s…
L6 Presentation
This is a relatively rare non-empty presentation layer on this site. Switch chips provide line-rate encryption offload, most typically MACsec — encryption at the Ethernet link layer — used to protect links between sites or facilities that traverse uncontrolled physical routes.
L7 Application
This layer is the chip's interface to the software world and the true source of this domain's commercial influence. A chip does not work by itself: a network operating system must configure its table entries and features through an SDK (software development kit), so the SDK's capability and openness directly determine whether third parties can build usable p…
Nvidia / Mellanox
Home turf: L2 / L4 / L7
L1 Physical
Why SerDes is the ceiling on chip bandwidth, and how higher rates shorten copper reach, are generic mechanics explained at L1 of this page's Broadcom domain and are not repeated. What characterises this domain at this layer is maintaining two physical-layer specifications in parallel: InfiniBand has its own complete physical layer and cabling ecosystem (its…
L2 Data Link
This is one of this domain's star layers, because at this layer it holds a technology route independent of Ethernet, its most fundamental difference from this page's Broadcom domain.
L3 Network
Layer-3 forwarding mechanics and table capacity constraints on the Ethernet side match those described at L3 of this page's Broadcom domain and are not repeated. What needs adding for this domain is that InfiniBand's routing model differs fundamentally from Ethernet's: rather than each node running routing protocols to convergence, a centralised subnet manag…
L4 Transport
This is this domain's second star layer and the most direct source of its contribution to this site's Neocloud category. The core of this layer is RDMA (remote direct memory access): letting one machine's NIC read and write another machine's memory directly, with the remote CPU taking no part at all.
L5 Session
This layer is explicitly empty — no product or service. This domain's products are chips and NICs, and it offers no session-layer product. It should be noted that although RDMA's queue pair is a communication-endpoint abstraction, it is a transport-layer mechanism (already recorded at L4) and is not double-counted here.
L6 Presentation
This is a relatively rare non-empty presentation layer on this site, comparable to this page's Broadcom domain but with a different emphasis. Beyond link-layer MACsec-class offload (mechanics at L6 of the Broadcom domain), this domain's DPU models can provide higher-layer encryption offload including IPsec and, on some models, TLS offload.
L7 Application
This is this domain's third star layer, because it holds two capabilities found nowhere else on this site. The first is the BlueField DPU (data processing unit): moving infrastructure software such as storage, security and network virtualisation off the host CPU to run on the NIC — the NIC contains independent general-purpose processor cores and an operating…
Marvell
Home turf: L1 / L2
L1 Physical
This is this domain's star layer and where it differs most from this page's Broadcom domain. Generic SerDes and PAM4 mechanics are at L1 of the Broadcom domain and are not repeated.
L2 Data Link
This is this domain's second star layer. What a switch chip does at layer 2 and the mechanics of the shallow-versus-deep buffer split are explained fully at L2 of this page's Broadcom domain and are not repeated.
L3 Network
The mechanics of layer-3 hardware forwarding, why table capacity is a hard budget fixed at chip design time, and how it determines whether a device can carry the full internet routing table are explained fully at L3 of this page's Broadcom domain; the mechanics are generic and are not repeated here.
L4 Transport
ECN and PFC mechanics on the switch-chip side match those described at L4 of this page's Broadcom domain and are not repeated. What this domain adds at this layer is the OCTEON series of multi-core network processors (from the 2018 acquisition of Cavium): not switch chips but processors embedding large numbers of general-purpose cores plus dedicated accelera…
L5 Session
This layer is explicitly empty — no product or service. This domain's products are chips and it offers no session-layer product. It should be noted that although the OCTEON series mentioned at L4 can perform stateful processing including connection-state tracking, that is software functionality its general-purpose programmable cores can host rather than a se…
L6 Presentation
This layer parallels this page's Broadcom domain: chips provide line-rate encryption offload, including MACsec on the switch-chip side and cryptographic accelerators embedded in the OCTEON series. MACsec's mechanics and the crucial 'link-level rather than end-to-end' boundary are explained fully at L6 of the Broadcom domain and are not repeated.
L7 Application
The mechanics and significance of SDKs and standard abstraction layers are explained fully at L7 of this page's Broadcom domain and are not repeated. What is genuinely distinctive for this domain at this layer is its custom silicon business for hyperscale customers: rather than selling standard models, it co-designs purpose-built chips with specific customer…
Intel Tofino
Home turf: L2 / L7
L1 Physical
There is no difference worth developing separately at this layer. Generic mechanics such as why SerDes is the bandwidth ceiling are at L1 of this page's Broadcom domain and are not repeated.
L2 Data Link
This is this domain's star layer and its entire reason for existing. Conventional switch chips are fixed-function: which protocol headers they recognise, in what order they parse them, and which actions they can take after a match are all hardwired into the pipeline at chip design time — supporting a new protocol means waiting for the next generation of sili…
L3 Network
Under this architecture, layer-3 forwarding is not a built-in chip function but part of the P4 program: longest prefix match, equal-cost multipath and tunnel encapsulation are all described by the user in the program and mapped onto match-action stages.
L4 Transport
This layer holds this domain's most practical legacy: In-band Network Telemetry (INT). L4 of this page's Broadcom domain mentions that in-band telemetry lets packets carry queue and latency information from each hop, and the maturation and spread of that practice is directly connected to this domain's programmable pipeline — because inserting custom metadata…
L5 Session
This layer is explicitly empty — no product or service. The reason matches this page's other silicon domains: a switch chip processes packets individually and maintains no application-level session concept.
L6 Presentation
This layer is explicitly empty — no product or service. This domain had no standalone encryption engine marketed as a product-line selling point: its value proposition concentrated on pipeline programmability, and encryption offload was not a direction of differentiation.
L7 Application
This is this domain's second star layer and contains two parts. The first is the P4 language and its ecosystem: P4 is a domain-specific language designed for packet processing, accompanied by compilers and standard control interfaces such as P4Runtime (letting a control plane uniformly read and write the tables defined in a P4 program).